1. Field of the Invention
The present invention relates to a semiconductor integrated device, more specifically, to a system-in-package type semiconductor device including a plurality of semiconductor chips to be operated by a plurality of power supplies.
2. Description of the Prior Art
Along with an increase in cell density of a semiconductor integrated device (hereinafter abbreviated as an “LSI”) and advance in the digital technology in recent years, circuits including digital circuits and analog circuits in single semiconductor devices are embedded in many products. In a digital camera or video equipment, for example, a DA converter and an AD converter for converting signals between analog signals and digital signals are embedded as a single semiconductor device.
Each of the digital circuit and the analog circuit embedded in the single semiconductor device is operated by a plurality of different power systems. Moreover, when the circuits operated by the plurality of different power systems are placed on the single semiconductor device, the semiconductor device requires a design in terms of electrostatic discharge (ESD) designing which is different from the ESD designing for a circuit including a single power system.
In particular, as miniaturization of an LSI progresses, the ESD designing in consideration of the miniaturization requires many processes at design and development stages. Accordingly, an increase in the development period is unignorable.
As described above, in order to prevent damage by electrostatic discharge in an LSI device including two or more sets of power supply wiring, there are known various aspects of inserting an ESD protection element between high-potential power supply wiring and a low-potential power supply wiring. A typical technique thereof is disclosed in Japanese Unexamined Patent Publication No. 9(1997)-172146, for example.
An LSI device in this prior art includes first and second power supply lines. Moreover, a high-potential side of the first power supply line and a high-potential side of the second power supply line are separated; meanwhile, a low-potential side of the first power supply line is coupled to a low-potential side of the second power supply line through a protection circuit (HK).
In this way, destruction of an element inside a second circuit attributable to a rise in electric potential on the low-potential side of the first power supply line is prevented. Besides, there are also known a technique to couple a high-potential side of a power system to a low-potential side of a different power system through a protection element, a technique to couple a protection element between a signal line of a first power system and a ground line of a second power system, and the like.
However, the present inventor has recognized that the prior part did not consider nodes of respective circuits on the high-potential side of the power supply line or on the low-potential side of the power supply line. Accordingly, this prior art causes variation of ESD tolerance and it is therefore difficult to manufacture an LSI with sufficient ESD tolerance.
Moreover, in terms of a circuit chip including an analog function cell and a digital circuit using different power supplies, there is also known a technique to insert a level conversion circuit for performing level conversion between an input/output signal of an analog function circuit and an input/output signal of the digital circuit, which is configured to draw in both of the power supply to be supplied to the analog function cell and the power supply to be supplied to the digital circuit. For example, the technique to insert the level conversion circuit is disclosed in Japanese Unexamined Patent Publication No. 10(1998)-150364.
The present inventor has recognized that this technique was a technique concerning optimization of a circuit area and was not designed in light of improvement in the ESD tolerance. Accordingly, occurrence of wiring resistance or wiring delay is unignorable, and the ESD tolerance is thereby varied.
SIP (System-in-package type semiconductor device) for mounting a plurality of chips on one package is noticed in addition to the SoC (System on Chip) technique for forming a plurality of different circuit portions in one chip. The SIP is provided with a plurality of chips and the chips are laminated or arranged in parallel in one package. The chips are connected through an inter-chip connection wiring. The inter-chip connection wiring is constituted of an internal wiring of an assembly substrate or a bump for directly connecting chips. In the case of the SIP, it is necessary to consider not only ESD current in a conventional chip but also ESD current flowing between chips.
Therefore, it is an object of the present invention to provide an LSI device, which is capable of effectively suppressing ESD destruction thereof.